A solid state drive (SSD) is a data storage device that utilizes solid-state memory to retain data in nonvolatile memory chips. NAND-based flash memories are widely used as the solid-state memory storage in SSDs due to their compactness, low power consumption, low cost, high data throughput and reliability. SSDs commonly employ several NAND-based flash memory chips and a flash controller to manage the flash memory and to transfer data between the flash memory and a host computer. SSDs may be used in place of hard disk drives (HDDs) to provide higher performance and to reduce mechanical reliability issues. An SSD includes a high-speed interface connected to a controller chip and a plurality of storage, or memory, elements. The controller chip translates a high-speed protocol received over the high-speed interface into the protocol required by the storage elements, which include solid state memory devices, such as semiconductor devices. The controller controls the occurrence of read and erase (i.e. program/erase cycles, or P/E cycles) events in the storage elements.
The storage elements in the SSD are organized into a plurality of blocks, which are the smallest erasable units in the memory device. The blocks are subdivided into pages, which are the smallest readable units of the memory device and the pages are subdivided into sectors. In a P/E cycle, all the pages in a block are erased and then some, if not all, of the pages in the block are subsequently programmed.
An issue for SSDs is the reliability of the storage elements over the life of the SSD. Over time, relatively high gate voltages applied to the storage elements during P/E cycles in the SSD may cause cumulative permanent changes to the storage element characteristics. Charge may become trapped in the gate oxide of the storage elements through stress-induced leakage current (SILC). As the charge accumulates, the effect of programming or erasing a storage element becomes less reliable and the overall endurance of the storage element decreases. Additionally, an increasing number of P/E cycles experienced by a storage element decreases the storage element's data retention capacity, as high voltage stress causes charge to be lost from the storage element's floating gate.
Because the cells become unreliable as a result of numerous program and erase (P/E) cycles and that the number of cycles that a single cell can sustain is limited, there is a need to avoid stressing particular blocks of cells of the memory device. Techniques known as “wear leveling” have been developed to evenly spread the number of P/E cycles among all of the available memory blocks to avoid the overuse of specific blocks of cells, thereby extending the life of the device. The goal of wear leveling is to insure that no single block of cells prematurely fails as a result of a higher concentration of P/E cycles than the other blocks of the memory storage device. Conventional wear leveling techniques arrange data so that P/E cycles are evenly distributed among all of the blocks in the device. The effect of wear leveling is to minimize the time between two consecutive P/E cycles for all of the blocks of the memory storage device to extend the useful life of the device. In addition to extending the useful life of the device, it is also desirable to minimize the Bit Error Rate (BER) of the data storage device. However, experimental measurements show that conventional wear leveling techniques may not be effective in minimizing the (BER) of the data storage device.
Accordingly, what is needed in the art is a system and method for wear leveling which also minimizes the BER of the data storage device.